1. Field of the Invention
The present invention relates to a scan flip flop circuit for allowing a test of a scan test scheme, which is incorporated in a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, semiconductor integrated circuits tend to have increasingly larger scales. Also, circuits with various functions such as adders, multipliers, RAMs, ROMs or the like have been incorporated in semiconductor integrated circuits.
In such a semiconductor circuit, an input signal is outputted via a number of functional circuits in the semiconductor integrated circuit, so that when malfunction occurs, it is difficult to presume in which functional circuit the malfunction occurs.
Thus, in the semiconductor integrated circuit in which a number of functional circuits are incorporated, for example, all or some of normal flip flops are replaced with scan flip flops and a test of a scan test scheme is performed with predetermined data set up in these scan flip flops to verify the circuit operation. In such a semiconductor integrated circuit, the circuit is operated in synchronization with a system clock for controlling the entire system during a normal operation. In contrast, the scan flip flop inputs, holds and outputs data for a scan test (scan in data) or an output of the functional circuit at the preceding stage to allow the test for the logical operation of each functional circuit during the scan test operation.
This type of circuit for performing the scan test is conventionally known as a scan flip flop circuit (hereinafter referred to as an SFF) and illustrated in FIG. 1.
This circuit comprises three latch circuits of a first through a third latch circuits. First latch circuit 114 is provided with data signal D and control signal CLK at data signal input terminal H01, and control signal input terminal H02, respectively, latches data signal D in synchronization with this control signal CLK, and delivers an output signal from data signal output terminal Q01. To transfer gates 91 and 92 are connected output P01 of inverter 110 and output P02 of inverter 111, respectively.
Second latch circuit 115 is provided with scan in data signal SIN and control signal SC1 at data signal input terminal H03, and control signal input terminal H04, respectively, and latches the scan in data signal SIN in synchronization with this control signal SC1, and delivers a second output signal from data signal output terminal Q03. To transfer gates 93 and 94 are connected both control signal input terminal H04 and output P03 of inverter 112.
Next, third latch circuit 116 consists of transfer gate 95 connected to data output terminal Q01 of first latch circuit 114, transfer gate 96 connected to data output terminal Q03 of second latch circuit 115, and further, transfer gates 97 and 98. Among them, to the transfer gates 95 and 97 are connected both outputs P01 and P02 similar to those used in first latch circuit 114, and to the transfer gates 96 and 98 are connected both control signal input terminal H05 inputted with control signal SC2 and output CB1 of inverter 113. Third latch circuit 116, when control signal SC2 is set up at a low level, latches the output signal of first latch circuit 114 in synchronization with control signal CLK and delivers output signals at data signal output terminals N01 through N03. Also, when control signal CLK is set up at a low level, third latch circuit 116 latches the output signal of second latch circuit 115 in synchronization with control signal SC2 and delivers output signals at data signal output terminals N01 through N03.
As described above, the conventional SFF circuit comprises three latch circuits. When this SFF circuit is assembled on a gate array with a substrate of a predetermined size, one cell is required for two transfer gates, one cell for each of output buffers 102 and 105 of the third latch circuit, and one cell for two inverters for the remaining ones. Thus, the circuit showed in FIG. 1 comprises 12.5 cells, or practically about 13 cells.
Next, the scan test operation of this circuit will hereinafter be described in reference to FIG. 1 and waveforms of the control signals as shown in FIG. 2.
First, a scan shift operation indicates that all sequential circuits are rearranged to form a SFF of register construction and scan in data is inputted from outside to be written to the SFF and the data of the SFF is outputted to the outside.
In second latch circuit 115, control signal SC1 is first inputted at 0 (low level) so that the transfer gate 93 is closed. Control signal SC1 is then changed to 1 (high level), transfer gate 93 is opened to fetch data SIN. Control signal SC1 is then changed to 0, transfer gate 93 is closed to open transfer gate 94 and data SIN is latched.
During this operation, in third latch circuit 116, control signal CLK is equal to 0 so that transfer gate 95 is closed and transfer gate 97 is opened. Also, transfer gate 96 is closed while control signal SC2 is inputted at 0. Then, control signal SC2 is changed to 1 and transfer gate 96 is opened to input the output signal of second latch circuit 115. When control signal SC2 is again changed to 0, transfer gate 96 is closed and transfer gate 98 is opened and then the inputted signal is latched and outputted from the output terminals.
In this way, the conventional SFF operates with the two-phase clocks of the SC1 and the SC2 during the scan shift operation.
Next, a scan normal operation will be described. The scan normal operation indicates that combination circuits of a semiconductor integrated circuit (portions excepting the SFF) are operated using an output value of the SFF and the result is written to the SFF.
In third latch circuit 116, control signal SC2 is inputted at 0 so that transfer gate 96 is closed and transfer gate 98 is opened. While control signal CLK is inputted at 0, transfer gates 91 and 97 are opened and the transfer gates 92 and 95 are closed, and the preceding cycle value is outputted.
Then, when control signal CLK is changed to 1, transfer gates 92 and 95 are opened, transfer gates 91 and 97 are closed, the inputted value is latched in first latch circuit 114, transmitted to third latch circuit 116 and outputted therefrom.
When the control C is changed to 0, transfer gates 91 and 97 are opened and transfer gates 92 and 95 are closed, the inputted value is latched in third latch circuit 116 and outputted therefrom.
In other words, during the scan normal operation, the SFF operates with the one-phase clock of the CLK.
In this way, the conventional circuit operates with the two-phase clocks of the SC1 and the SC2 during the scan shift operation, and operates with the one-phase clock of the CLK during the scan normal operation. It should be noted that the conventional circuit also operates with the one-phase clock of the CLK during a user mode because it operates as a normal flip flop.
When the scan circuit is incorporated in an integrated circuit, the most difficult problem is that the area of the integrated circuit is increased as the scan circuit is incorporated in an ordinary circuit. For example, though an ordinary circuit can be formed using a substrate with a predetermined size, a circuit having an incorporated scan circuit may have to be formed using a substrate greater than that for the ordinary circuit, resulting in an increased cost. The scan circuit is classified roughly into a control circuit, a simultaneous operation control circuit and an SFF, and the SFF has the greatest effect on the area of the circuit among them. Thus, it is important to minimize the area of the SFF.
In addition, when the one-phase clock is used in the scan operation of a circuit, the adjustment of clock skew is required for a normal operation of the circuit. The clock skew is a delay of the clock due to wiring delay and so on. In recent years, the method which utilizes a CTS is widely used for adjusting the clock skew. In the CTS, as described simply, buffers are provided on the way of the clock distribution lines, or the length and the shape of the clock distribution lines are arranged so that the clock skew becomes uniform. The details of the CTS are described in LSI LOGIC LCA 500K, Preliminary Design Manual, Chapter 8. However, even though the use of the CTS causes the skew to be decreased, a number of flip flops may operate at the same time to make it difficult to perform the scan shift operation due to the power noises.
Further, when a user uses a plurality of clocks and the waveforms of the clocks are different one another, the same waveform is inputted to the clock terminals of all the SFFs during the scan normal operation since the one-phase clock is used, and, therefore, the circuit may not operate normally because a data passing through without latching occurs.
In the scan test, the FFs (flip flop) are replaced by the SFFs. Since the replacement is usually done after a design of all of circuits is finished, it is important that a time-delay in the user logical portion is not changed. However, the time-delay is changed in many cases since the SFFs are formed by adding a scan function to the usual FFs, and a readjustment of the time-delay was necessary for the user circuits after the replacement.